The advancement of computing technology is spurred on, in large part, by the desire to improve performance. However, performance increases do not always require bigger and faster devices. Enhanced performance may also be derived by improving the way in which operations are performed. For example, during normal operation a processor may read data from, and write data to, a memory in a computing device. In the most basic sense, the performance (e.g., speed) of the read and write transactions may be defined by the speed of the processor and the memory. However, the speed at which these components communicate may also be increased through the introduction of intermediate resources that help to facilitate the interaction. For example, a cache memory may be a smaller and/or faster memory accessible by the processor to store information frequently accessed by the processor. The cache may increase the speed at which operations are performed on the computing device because the processor doesn't have to constantly access the main memory. Instead, needed data may be more quickly accessible from the cache memory.
However, an insatiable desire for increased performance has yielded new opportunities to eke out even more speed. For example, an area where an opportunity for improvement has been identified is the manner in which a processor may interact with a cache memory. Previously, processors including a plurality of cores with each core possibly executing a separate thread that may be writing the same cache memory would have to first determine the owner (e.g., the thread) of particular sections of the cache memory so that data already existing in the cache memory would not become corrupted. Emerging processors are now being equipped with data transactions that allow entire cache-lines of data to be written without first having to verify ownership of the section of cache memory. The use of these new data transactions may substantially increase the rate at which data can be written by a processor to cache memory, and thus, may substantially increase overall system performance. However, at least one impediment to the use of these new data transactions is the rigid conditions that need to exist before the transaction may be used, limiting any performance increase that may be realized.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art.